ENGINEERING SERVICES EXAM 2012 - PART II
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11) Assuming that only logic inputs X and Y are available and their complements
X' and Y' are not available, the minimum number of two-input NAND gates required to implement X xor Y would be
X' and Y' are not available, the minimum number of two-input NAND gates required to implement X xor Y would be
(a) 2 (b) 3 (c) 4 (d) 5
Solution
F = X XOR Y
= X’Y+ XY’
= X’Y + XY’+ XX’ + YY’ (because XX’ = YY’ = 0)
= (X + Y) (X’ + Y’) (rearranging and combining)
= (X+Y)(XY)’ (By DeMorgan’s theorem)
= X. (XY)’ + Y. (XY)’
Taking complement of above function
F’=
( X. (XY)’ + Y. (XY)’ )’
= (X. (XY)’)’. (Y. (XY)’)
Complement again to get original function
F=
( (X. (XY)’)’. (Y. (XY)’) )’
Therefore the minimum number of two-input NAND gates required = 4
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12) The minimum number of NAND gates required to implement A+ AB'+AB'C is equal to
(a) Zero (b) 1 (c) 4 (d) 7
Solution
F = A+AB’+AB’C
= A+AB’(1+C) (because 1+C = 1, in Boolean algebra)
= A+AB’
= A(1+B’)
= A
Minimum number of NAND gates
required = 0
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13) The threshold effect in
demodulators is
(a) The rapid fall of output SNR
when the input SNR falls below a particular value
(b) Exhibited by all the
demodulators when the input SNR is low
(c) Exhibited by all AM
suppressed carrier coherent demodulators
(d) Exhibited by correlation
receivers
Solution
FM demodulation is completely a
non linear process in which input additive signal and noise components results
in additive demodulated signal and noise output. This statement is held true if
and only if S/N ratio of input is sufficiently high(above threshold SNR).Below
threshold SNR output of demodulator will not be in additive form and will be so
intermingled that we cannot recognize signal from noise. This leads to a rapid
fall in SNR of output and is called threshold effect.
Answer is (a)
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14) In communication systems, noise due to quantization error is
(a) Linear and signal dependent
(b) Non-linear and signal dependent
(c) Linear and signal independent at low frequencies only
(d) non-linear and signal dependent at low frequencies only
Solution
The effects of quantisation error
are in fact both non linear and signal dependent. Non linear means we cannot
calculate their effects using normal maths. Signal dependent means that even if
we could calculate their effect, we would have to do so separately for every
type of signal we expect. The only the only reliable way to check it is to
implement a system , and test it against signals of the type expected.
For explanation click here
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15) A small code of 8085 as given
below, is executed
MVI A, 7FH
ORA A
CPI A2H
The contents of the accumulator
and flags after execution are
(a) A = DD, S = 1, Z = 0, CY = 0
(b) A = 7F, S = 1, Z = 0, CY = 1
(c) A = DD, S=0, Z= 1, CY =0 (d) A = 7F,
S = 0, Z = 1, CY = 1
Solution
MVI A, 7FH => A contains 7F
ORA A => contents of A are ORed with
itself and stored in A, so A contains 7F
CPI A2H => The value of A is compared with
immediate value, but value of A is unaltered only flags will change in value
7F=> 0111 1111
A2=>1010 0010
Compare=> 7F-A2 = DD (with a
borrow)
Value at A is unaltered by the above
operation, A=7F
CY bit is changed because there is carry
generated from subtraction, CY=1
Z is the zero bit,Z=0
S is the sign bit and S=1 because
compared output is negative
answer is (b)
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16) An Intel 8085 processor is executing the program given below:
MVI A, 10H
MVI B, 10H
BACK : NOP
ADD B
RLC
JNC BACK
HLT
The number of times that the operation NOP will be executed as
(a) 1 (b) 2 (c) 3 (d) 4
Solution
A= 0001 0000
B=0001 0000
LOOP1-steps
NOP ------(1)
A+B = 0 | 0010 0000
Rotate Left with Carry => CY=0, A=0100 0000
Jump on Not Carry=>CY=0,LOOP AGAIN
LOOP2-steps
NOP ------(2)
A+B= 0 | 0101 0000
Rotate Left with Carry => CY=0, A=1000 0000
Jump on Not Carry ,CY=0,LOOP AGAIN
LOOP3-steps
NOP ------(3)
On this RLC step CY becomes 1,So JNC condition
fails and program execution stops.
The number of times NOP will be executed is 3
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17) While executing a program, 8085 microprocessor completes fetching of instruction JMP 2050 stored at address 2057H. The contents of the program counter after fetching the instruction would be
(a) 2050H (b) 2057 H (c) 205A H (d) 2051 H
Solution
Program Counter(PC) points to the address of next
instruction to be fetched.
Here JMP 2050 is at location 2057.
This means,
JMP will be at 2057 (8
bit instruction)
20 will be at 2058
50 will be at 2059
The next instruction will be at 205AH.
It is not 2050 because only after execution phase
the processor will decide whether to take the jump or not. PC will be set long
before the execution of previous instruction. So only after the execution phase
of JMP 2050 it will save current PC and load the new value of 2050.
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18) A memory system has a total of 8 memory chips, each with 12 address lines and 4 data lines. The size of the memory system is
(a) 16k bytes (b) 32k bytes (c) 48 k bytes (d) 64k bytes
Solution
There are 8 chips. Only 1 chip can be used at a
time, for selection of 1 out of 8 chips we need 3 selection lines (chip select).
000 => first chip
001 => second chip
.
.
111 => eighth chip
Address lines remaining = 12-3=9
So for each chip there will be 29 = 512 memory
locations
For 8 chips 512 x 8 =4098 memory locations
There are only 4 data lines, each location can have
a maximum of 4 bits only which can be read simultaneously
Therefore size of memory system = 4098 x 4 = 16k
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19) The incorrect match (when n > 1) is
(a) SISD Model of computer : 1 control unit and 1 ALU
(b) SIMD Model of computer : 1 control unit and n ALUs
(c) MISD Model of computer : n control units and n ALUs
(d) MIMD model of computer : n control units and 1 ALU
Solution
Single Instruction, Single Data – It has a single processor which executes a single instruction at a time on a single data stream.
Single Instruction, Multiple Data – It has multiple processing units which executes a single instruction at a time on multiple data streams. An application that may take advantage of SIMD is one where the same value is being added to (or subtracted from) a large number of data points, a common operation in many multimedia applications. One example would be changing the brightness of an image. Each pixel of an image consists of three values for the brightness of the red (R), green (G) and blue (B) portions of the color. To change the brightness, the R, G and B values are read from memory, a value is added to (or subtracted from) them, and the resulting values are written back out to memory.
Multiple Instruction, Single Data – This is a type of parallel computing architecture where many functional units perform different operations on the same data. Pipeline architectures belong to this type, though a purist might say that the data is different after processing by each stage in the pipeline. It requires n control units to decode n instructions, and n ALUs for doing operations on single data at ‘n’ processing units.
Multiple Instruction, Multiple Data – Machines using MIMD have a number of processors that function asynchronously and independently. At any time, different processors may be executing different instructions on different pieces of data. MIMD architectures may be used in a number of application areas such as computer-aided design/computer-aided manufacturing, simulation, modelling, and as communication switches. It requires n control units to decode n instructions, and n ALUs for doing operations on n datastreams at ‘n’ processing units.
For more details with diagrams click here
Answer is (d)
Single Instruction, Multiple Data – It has multiple processing units which executes a single instruction at a time on multiple data streams. An application that may take advantage of SIMD is one where the same value is being added to (or subtracted from) a large number of data points, a common operation in many multimedia applications. One example would be changing the brightness of an image. Each pixel of an image consists of three values for the brightness of the red (R), green (G) and blue (B) portions of the color. To change the brightness, the R, G and B values are read from memory, a value is added to (or subtracted from) them, and the resulting values are written back out to memory.
Multiple Instruction, Single Data – This is a type of parallel computing architecture where many functional units perform different operations on the same data. Pipeline architectures belong to this type, though a purist might say that the data is different after processing by each stage in the pipeline. It requires n control units to decode n instructions, and n ALUs for doing operations on single data at ‘n’ processing units.
Multiple Instruction, Multiple Data – Machines using MIMD have a number of processors that function asynchronously and independently. At any time, different processors may be executing different instructions on different pieces of data. MIMD architectures may be used in a number of application areas such as computer-aided design/computer-aided manufacturing, simulation, modelling, and as communication switches. It requires n control units to decode n instructions, and n ALUs for doing operations on n datastreams at ‘n’ processing units.
For more details with diagrams click here
Answer is (d)
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20) A communication link is to be set up better two stations 100km as part using λ/2 antenna to transmit 1kW power. The operating frequency is 100 MHz and the directivity of the two antennae is 1.64. The maximum received power would be
(a) 3.06 x 10-8 W (b) 1.53 x 10-8W (c) 6.12 x 10-8W (d) 1 x 10-8W
Solution
The expression for recieved power is given by
$$P_{R}= \frac{P_{T}G_{T}G_{R}c^{2}}{(4\pi Rf)^{2}}$$
where
PR – received power
PT – transmitted power
GR – receiver antenna directive
gain (or directivity if we want maximum power)
GT – transmitter antenna directive
gain (or directivity if we want maximum power)
C – velocity of light
R – distance between transmitter and receiver
f – frequency of transmitted wave
For detailed explanation of above formula click here
Substituting for all unknowns answer is (b)
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