GATE 2012 ECE paper fully solved.Step by step, detailed solutions are given.Corrections and suggestions are appreciated.
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1) The current ib through the base of a
silicon npn transistor is 1+0.1 cos(10000πt)
mA. At 300 K, the rπ
in the small signal model of the transistor is
(A) 250 Ω (B) 27.5 Ω (C) 25 Ω (D) 22.5 Ω
Solution
rπ = β/gm
gm =
Ic/VT
substituting
second equation in first
rπ = β / (Ic/VT)
= β VT/ Ic
= (β/Ic )VT
= VT / Ib (because Ic = βIb,
So 1/Ib = β/Ic)
= 25mV/1mA (
Ic=1mA)
= 25 Ω
2) In a baseband communications
link, frequencies upto 3500 Hz are used for signalling. Using a raised cosine
pulse with 75% excess bandwidth and for no inter-symbol interference, the
maximum possible signalling rate in symbols per second is
(A) 1750 (B) 2625 (C)
4000 (D) 5250
Solution
Raised cosine filter is an
example of Pulse shaping filter. Pulse shaping is the process of changing the
waveform of transmitted pulses. Its purpose is to make the transmitted signal
better suited to its purpose or the communication channel, typically by
limiting the effective bandwidth of the transmission. By
filtering the transmitted pulses this way, the InterSymbol Interference caused by the
channel can be kept in control.
The roll-off
factor, β, is a measure of the excess bandwidth of the filter, i.e. ratio of the
excess bandwidth occupied to the Nyquist bandwidth B
Bandwidth B = 3500 Hz
ie; β = Δf/B = 0.75
(given)
Also Bandwidth B is defined by
B = RS(β+1)/2
Where RS is the symbol
rate
3500 = RS(0.75+1)/2
RS = 7000/1.75= 4000
3) The
i-v characteristics of the diode in the circuit given below are
The current in the circuit is
(A)
10 mA (B) 9.3 mA (C) 6.67 mA (D) 6.2 mA
Solution
Applying
KVL in the loop
10
- 1000i - v = 0
10
- 1000*[(v - 0.7) / 500] - v = 0
10
- 2(v - 0.7) - v = 0
10
- 2v + 1.4 – v = 0
v
= 11.4 / 3 = 3.8
Now, i = (v - 0.7) / 500 (given)
= (3.8 - 0.7) / 500
= 6.2 mA
4) The average power delivered to an impedance (4 - j3)Ω by
a current 5cos(100p t +100) A is
(A) 44.2
W (B) 50 W (C) 62.5 W (D)
125 W
Solution
I = 5cos(100p t +100) A
Irms=
I peak/√2
= 5 /√2
Z = (4 - j3) W
Average power= (Irms)2 *R (R is the real part
of Z)
=(25/2)*4
= 50W
5)
The diodes
and capacitors in the circuit shown are ideal. The voltage v(t)
across the diode D1 is
(A) cos(wt) -1
(B) sin(w t) (C) 1-cos(wt) (D) 1-sin(wt)
Solution
The C1 and D1 acts as a negative clamper.
During positive cycle of coswt, D1 is forward biased capacitor
left plate charges to +1V. So on right plate of C1 voltage will be -1V.This is
the DC shift value of clamper. During negative cycle diode is reverse biased
and capacitor retains DC value.
The output of clamper section will be dc value + ac value
riding over it i.e.; -1+coswt or (coswt-1).
C2, D2 section is a filter which allows only negative cycles
to pass through. But our waveform (coswt-1)
contains negative values only and it is passed through filter as such.
Output is (coswt-1)
6) The impedance looking into nodes 1 and 2 in the given circuit is
(A) 50 ohm (B) 100 ohm (C) 5 K (D) 10.1 K
Solution
The circuit given is in CC configuration
(no collector resistance).
β = 99 (given)
We have to find impedance in
emitter side. There is already one 100ohm at emitter and there is a 9k and 1k
in the base side.
Base resistance 9K + 1K = 10K because
they are in series
But this 10K and emitter 100ohm
are not in series because former is in base terminal where Ib is the
current and latter is in emitter side where Ie is the current.
So we have to move this 10K to
emitter side first. For that we have to divide it by β+1(using
impedance reflection, and Ib = Ie/ (β+1))
Moving 10K to emitter = 10K /β+1 = 10K / 100 = 100ohm
Now this
100ohm is in parallel with emitter’s 100ohm,
So equivalent
resistance at emitter(between terminals 1 and 2)
=100||100 = 50 ohm
7) Consider the given
circuit.
In this circuit, the race around
(A) does not occur (B) occurs
when CLK = 0
(C) occurs when CLK = 1 and A = B = 1 (D) occurs when CLK = 1 and A = B = 0
Solution
(A)
Race around occurs in JK
flip flop.
The given flip flop is SR.
8) The output Y of a 2-bit comparator is logic 1
whenever the 2-bit input A is greater than the 2-bit
input B. The number of combinations for which the
output is logic 1, is
(A) 4 (B)
6 (C) 8 (D) 10
Solution
Two bit numbers A and B
A B A>B
00 00 0
01 01 1 (when
A=01, B=00)
10 10 2 (when
A=10, B=00, 01)
11 11 3 (when
A=11, B=00, 01, 10)
A>B can occur 0+1+2+3 = 6
times
9) In the circuit
shown
_ _ _
(A) Y = A
B +C (B) Y = (A+ B)C
_ _ _
(C) Y = (A + B)C (D)
Y = AB
+C
Solution
CMOS circuit given is
______
Y= A+B.C
____ _
Y= A+B + C (Using De Morgan’s
theorem)
_ _ _
Y= A . B + C (Using
De Morgan’s theorem)
10) A source alphabet consists of N symbols with
the probability of the first two symbols being the same. A source encoder increases the probability of
the first symbol by a small amount e and decreases that of the second by e . After encoding, the entropy of
the source
(A) increases (B)
remains the same
(C) increases only if N = 2 (D) decreases
Solution
Maximum Entropy is obtained
when all symbols have same probability.
Here we are changing two
equiprobable symbols to distinct ones. So always entropy will decreases
compared to previous case.
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